When investigating the operation of a computer architecture (i.e., troubleshooting or debugging the system hardware or software), it is commonplace for an engineer to employ a logic analyzer to capture data traffic on the system bus. This may be done by unplugging an IC processor from its socket, plugging in a probe adapter, and reinstalling the processor in a socket of the probe adapter. In this way, the logic analyzer gets access to the system (i.e., computer) bus without disabling the operation of the device under test (DUT).
Modern computers require high-speed communication between such integrated circuits (i.e., IC's or “chips”) residing on a bus. This high-speed communication entails bidirectional data transfers on the order of 400 Mb/s (Megabits per second) or greater per channel. Data, clock, and strobe signals are usually sent from a source IC to the destination IC to accomplish these data transfers.
At these high data rates, UHF RF (ultra high frequency radio frequency) circuit board design rules apply to the physical layout of the computer bus. At these RF frequencies, the physical length of a bus line affects the “flight time” of the signals from a source IC to a destination IC. Therefore, under such rules, the physical length of each clock, data, and strobe line is carefully assigned to ensure that the signals arrive at the destination IC with the proper timing relationship.
Because the above mentioned probe adapter is plugged into a single fixed IC processor location, it follows that signals sent to that location will be received by the logic analyzer probe with the proper timing relationship. However, these timing relationships may be violated when the processor in the probe adapter drives the bus. Under these conditions, the aforementioned timing relationships (bus latency) do not hold.
A logic analyzer monitoring bus traffic faces yet another signal timing problem. Some microprocessor buses implement a technique known as strobe phase reversal. The following brief explanation may be helpful in understanding this problem.
In order for microprocessor vendors to increase the throughput of data transfer on microprocessor buses, the rate at which data is presented on the bus must be increased. One method to do this is to increase the number of times data is presented on the bus in one clock cycle. In order to better control the timing and latching of this data, separate data strobes are provided that can be used as data login latch signals to latch the data as they are presented on the data bus. FIG. 1 shows an example of a normal data transfer. In this example, data is transferred once in one clock cycle. The timing of the data is referenced to the clock signal. While this transfer method has been widely used, it tends to be too slow for today's high-speed applications.
In a source-synchronous system, data is output two or more times during one clock cycle, thus increasing the data throughput by a factor of at least two. FIG. 2 is an example of a 2× data bus transfer. In this example, data is transferred twice during one clock cycle. The timing of the strobe is centered in the data valid window. Although the data timing is referenced to the strobes, the data is eventually synchronized to the clock signal at a later time by the receiving device. Such a bus is known from the Itanium® computer bus architecture, developed and manufactured by Intel Corporation, Hillsboro, Oreg.
As can be seen in FIG. 2, two strobes are employed in this system, STBp and STBn. Strobes STBp and STBn are pseudo-differential signals, as opposed to true differential signals, in that strobes STBp and STBn can assume an idle state in which both signals are at a high logic level. In the example of FIG. 2, the falling edge of the strobe signal STBn is used to latch DATA 1, DATA 3, and DATA 5. The falling edge of strobe signal STBp is used to latch DATA 2, and DATA 4. In other words, strobe STBn is used to latch the odd data transfers, and strobe STBp is used to latch the even data transfers. Thus, the data transfer scheme of FIG. 2 effectively doubles the data transfer rate with respect to the scheme used in FIG. 1.
After the processor finishes transferring data (i.e., “driving” the bus), it must release the bus for use by others. Following the transfer of DATA 5, there is a period 210 during which there is no valid data on the bus. Releasing the bus is accomplished by providing a positive-going “post-drive” transition 220 on whichever strobe (STBp or STBn) happens to be in its low logic level state, to drive it to the high logic level state. The strobes STBp and STBn are now both at a high logic level indicative of the idle state mentioned above.
In some microprocessor systems employing this 2× mode data transfer technique, the polarity of the strobes can be reversed between data transfer cycles. The purpose of this strobe polarity reversal is to reduce the latency between data transfers. FIG. 3 shows an example of an occurrence of a strobe phase reversal on the bus, and an example of a strobe state in which a processor is maintaining control of the bus.
Referring to FIG. 3, during period 310, there is no valid data on the bus. However, the processor currently in control of the bus wishes to retain control. The processor keeps control by maintaining common clock control signals in their present states which results in strobes STBp and STBn being maintained in their respective present states at points 315 318. Note that the strobes are in their proper states to enable the latching of DATA 1 without delay.
After the completion of the transfer of DATA 2, there is no valid data on the bus (i.e., during period 330), and the processor releases the bus by providing a positive-going post-drive transition on Strobe STBn at point 338. At point 340, a different processor provides a negative-going pre-drive transition on Strobe STBp. This pre-drive transition places the strobes into the differential relationship with respect to one another in preparation for latching the next valid data (DATA 1′ in this example). It is important to note that since data capture is controlled by negative-going edges of the strobes, the predrive transition causes an erroneous acquisition of invalid data.
Note that a strobe phase reversal has occurred. Before the strobe phase reversal had occurred, the falling edge of STBp had been associated with the odd data transfers and the falling edge of STBn had been associated with the even data transfers. After the strobe phase reversal occurred, the falling edge of STBp became associated with the even data transfers, and the falling edge of STBn is now used to latch the odd data transfers.
If a microprocessor probe is latching this data into memory devices such as flip-flops, a strobe phase reversal will cause the data to be presented to the Logic Analyzer in a swapped order and may also result in an extra data sample. One may think that a good solution to this problem would be to program the Logic Analyzer to reorder the data. However, this solution is undesirable for at least three distinct reasons. First, this solution puts an extra burden on the disassembly software in the Logic Analyzer to reorder the data whenever a strobe phase inversion takes place. In such a system, inverse assembly software manipulates the data based on stored flag information to determine when a strobe phase reversal had occurred. This extra burden causes a significant increase in the time it takes the microprocessor disassembly software to present to the user the transactions that are occurring on the data bus. Second, this solution doesn't store the data as it was transferred across the bus. Third, this solution operates in a post-processing mode; it does not operate in real time. Since triggering must occur in real time, using this scheme would make it difficult, if not impossible, to trigger on data affected by such a strobe phase reversal.
What is needed is a logic analyzer probe apparatus and method that resolves any observed improper timing relationships and properly acquires substantially all bus transactions even when a phase reversal occurs.